Summary
Overview
Work History
Education
Skills
Software
Certification
Timeline
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Jorge Blanco

Physical/Structural Design Engineer
Vitacura

Summary

Senior Electrical Engineer at Universidad de Costa Rica with a mid-level technical degree in industrial electronics.

Experienced Structural/Physical design engineer with over seven years of experience on VLSI Design methodologies, eager to contribute to team success through hard work, attention to detail and excellent organizational skills. Highly hands-on experience in sub-block and macro-block Floor-planning and Physical verification, P&R, timing closure, formal verification, power planning and ECO flows. As well knowledge of Synopsys EDA tools and Linux, python and TCL scripting skills. Good debugging skills with high sense of responsibility, able to work under pressure both individually and as part of a team.

Collaborative administrative leader with dedication to partnering with coworkers to promote engaged, empowering work culture. Determined and experienced in mentoring and challenging team members to meet and exceed company goals.

Overview

15
15
years of professional experience
1
1
Certification
2
2
Languages

Work History

Staff Application Engineer

Synopsys
01.2023 - Current
  • Responsible for providing customers technical supports and consultant services through projects collaboration, improving power, performance and area metrics for customer's designs.
  • Conducted thorough root cause analysis on reported issues, resulting in prompt resolution of critical bugs.
  • Help on successful migration of applications to cloud-based infrastructure and different tool versions, resulting in increased scalability, runtime and cost savings for customer.
  • Championed continued education among teammates by sharing industry trends and new technologies during team meetings or informal discussions, growing-up technical level of entire team.

Graphics Structural Design Engineer

Intel
5 2021 - 12.2022
  • Structural design for discrete and client graphics products, including timing (transition, hold and setup violations)/routing closure, ECO implementation and multiple quality rule convergence like power delivery network, low power verification, physical verification, and logical equivalence checks for many blocks, on 10nm/7nm/5nm/4nm/3nm technologies.
  • Proved successful working within tight deadlines and fast-paced atmosphere until Tape-Ins.
  • Managed team of junior employees, overseeing hiring, training and professional growth of these employees.

Physical Design Engineer

Intel
03.2015 - 05.2021
  • Planning, auto-place and route, physical verification (DRC/LVS convergence), signal integrity and power analysis, formal and reliability verification, and physical layout verification at block and/or macro block level in 28nm/14nm/10nm/7nm/5n/3nm technologies.
  • Strong technical knowledge and Tape-in/Tape-out experiences of several quantity of projects.
  • Good working experience with tools like ICC/ICC2/Fusion Compiler, PT, ESP (by Synopsis) and automation skills scripting on python and TCL languages.
  • Collaborated with team members to achieve target results. Besides, actively worked on creation and development of training materials for technical growth of new hires.

Electronics technician

Proveeduría Total de Servicios
08.2009 - 03.2011
  • Assembled of automobile maintenance equipments according to engineering data and knowledge of electrical principles, using hand tools and measuring instruments.
  • Fixed circuit boards and wire harness problems using schematics, wiring diagrams and testing instruments.
  • Educated equipment operators and clients on proper use of equipment.

Education

Bachelor of Science - Electrical, Electronics Engineering Technologies

Universidad De Costa Rica
San Pedro De Montes De Oca, Costa Rica
03.2011 - 2016.03

Mid-Level Technical Degree - Industrial Electronics

Colegio Vocacional De Artes Y Oficios
Cartago,Costa Rica
01.2003 - 2005.01

Skills

    Critical Thinking

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Software

Synopsys EDA Tools

Python, TCL, C

Unix

Assembly, MatLab, Verilog

Microsoft Office, GIT Tools, MySQL

Certification

Synopsys Purple Certification

Timeline

Synopsys Purple Certification

05-2024

Staff Application Engineer

Synopsys
01.2023 - Current

Physical Design Engineer

Intel
03.2015 - 05.2021

Bachelor of Science - Electrical, Electronics Engineering Technologies

Universidad De Costa Rica
03.2011 - 2016.03

Electronics technician

Proveeduría Total de Servicios
08.2009 - 03.2011

Mid-Level Technical Degree - Industrial Electronics

Colegio Vocacional De Artes Y Oficios
01.2003 - 2005.01

Graphics Structural Design Engineer

Intel
5 2021 - 12.2022
Jorge BlancoPhysical/Structural Design Engineer